This invention relates in general to semiconductor structures and in particular to semiconductor structures with slew-rate control.
Semiconductor devices employ output buffers for driving external circuits. The switching currents present in such devices when they are changing states is the major source of noise spikes on power busses. This noise can cause erroneous switching in TTL logic buffers and other clocked macrocells. Also this noise can induce latch up to other driven chips. These output devices are frequently required to drive heavy loads. For this reason such devices frequently have to meet certain DC drive requirements. Hence, even though noise spikes can be reduced by reducing the size of these output devices, smaller devices are not capable of driving the heavy loads required. It is therefore desirable to provide slew-rate control to slow down the output devices in a manner that will reduce the rate of change of output voltage and peak current value while maintaining the DC output drive capability of these devices.
Slew rate is defined as the rate of output transition in volts per unit time. For output devices to have high DC drive capability, these devices normally employ two or more elements placed in parallel. Conventional slew rate control employs delay elements between parallel devices.
The inclusion of delay elements requires a considerable amount of area in the semiconductor medium in which the output device is implemented. This area penalty becomes increasingly more costly as the output area becomes the size limiting factor in submicron technology due to the fact that the ESD area requirements are non-shrinkable and most circuit architectures become pad limited. It is therefore desirable to provide semiconductor structures with slew-rate control where the above-described difficulties are alleviated.